The present invention relates to digital logic arrays, and more particularly, to a storage cell for a storage logic array.
Programmable logic arrays are one method by which manufacturers can provide complex electronic circuitry on semiconductor chips. Programmable logic arrays are one member of a broader class of devices known as "semicustom integrated circuits." A semicustom integrated circuit is a device which can easily be "personalized" to provide desired functions. Masterslices, uncommitted logic arrays, gate arrays and macrocell arrays are different types of semicustom integrated circuits.
A gate array typically consists of a plurality of cells which can be interconnected to form different electronic circuits, each circuit performing a specific function.
Macrocell arrays are formed from cells that are more sophisticated than those used in simple gate arrays. These "macrocells" contain electronic circuitry which is capable of performing complete predefined functions.
An uncommitted logic array ("ULA") contains transistors arranged in a repetitive pattern on a silicon chip. The actual interconnections between the transistors are not made initially. Instead, the unconnected transistors in a standard ULA are connected during a final processing step which will determine the actual circuit functions that the ULA will perform. The ULA transistors can be connected to form any logic function, at will. These logic functions can be further connected to form more complex circuitry.
By contrast, a programmable logic array ("PLA") is usually constructed in the form of two arrays. One array, known as an AND array, forms a predefined output when all of its input data is at a proper level. The other array is known as an OR array and combines information from selected AND arrays to form outputs. The PLA is programmed by connecting predetermined input lines to the AND arrays and interconnecting appropriate AND and OR arrays.
One drawback to PLAs is that the amount of useful circuitry in them is limited by the number of input and output pins which can be placed in a standard integrated circuit package. Since the inputs to the AND array originate outside the integrated circuit chip, pins must be provided on the integrated circuit package to connect signals external to the chip to the circuitry inside the chip. Similarly, pins must be provided on the integrated circuit package to connect the outputs from the integrated circuitry to other circuitry external to the chip. Physical size limitations of the integrated circuit package dictate the number of such input and output pins which can be provided.
In response to such pin limitations, a specialized form of PLA, known as a storage logic array ("SLA"), has been developed. In an SLA, "storage cells" having memory capacity are provided to temporarily store interim calculations. In this manner, data generated within the SLA for use in subsequent operations of the SLA can be retained therein. Input and output pins are not wasted in transmitting such data out of the chip and then back into it for subsequent reuse. The data is simply maintained within the chip until it is no longer needed.
In a storage logic array, a specific type of memory element known as a flip-flop is generally used. Flip-flops are electronic circuits which change their output state, e.g. from a high level to a low level, in response to a predetermined input signal. The output of a flip-flop, once set at a given level, will remain at that level until reset by another input signal. Thus, a flip-flop functions as a memory element because once its output is set to a given level, it remembers and maintains that level until it is reset at a later point in time.
The general design and operation of a storage logic array is disclosed in U.S. Pat. No. 4,068,214, issued to Suhas S. Patil on Jan. 10, 1978. A good explanation of SLAs can also be found in the article "A Programmable Logic Approach for VLSI", S.S. Patil and T. A. Welch, IEEE Transactions on Computers, Vol. C-28, No. 9, September 1979, pages 594 to 601.
The storage logic array basically comprises a plurality of orthogonally disposed column and row conductors having "cells" connected thereto. Two classes of cells are used in conjunction with SLAs. Storage cells are those which contain memory elements such as the flip-flops described above, and are physically placed within SLA columns. Logic cells are relatively simple electronic circuit building blocks which are used to interconnect rows and columns of the SLA.
By arranging logic cells to interconnect columns and rows in accordance with one or more predetermined logical functions, the SLA can produce predetermined output signals in response to a predetermined input signal or set of signals. One advantage of SLAs is that selected columns and rows of the array can be subdivided into multiple independent sections which each perform different tasks. For example, one section of the array can be used to build a functional electronic circuit known as a register. Another section can be built to function as control circuitry, and a third independent section can be used to build an electronic adder to add numbers together. Specific flip-flops internal to each of these independent functional sections are used to store data generated within the section.
It should now be appreciated that an SLA is constructed of columns, rows, logic cells which interconnect selected columns and rows, and storage cells within the columns.
Past SLA designs have incorporated a storage cell having a memory element that required four separate conductors to get data into and out of the flip-flop. In these prior art arrangements, separate conductors are used for each of the two flip-flop inputs (known as the reset ("R") and set ("S") inputs) and each of the two flip-flop outputs (known as the "Q" and "Q" outputs). Data is transferred into the flip-flop by means of the S and R input conductors. Data is transferred from the flip-flop by means of the Q and Q output conductors.